A Framework for the Detection of Crosstalk Noise in FPGAs

In recent years, crosstalk noise has emerged a serious problem because more and more devices and wires have been packed on electronic chips. As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is the important phenomenon that must be taken into account. Despite of being more immune to crosstalk noise than their ASIC (application specific integrated circuit) counterparts, the dense interconnected structures of FPGAs (field programmable gate arrays) invite more vulnerabilities with crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults affected by crosstalk noise. This paper proposes a new approach for detecting the effects such as glitches and delays in transition that are due to crosstalk noise in FPGAs. This approach is similar to the BIST (built-in self test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any overhead for testing

Testing of Asynchronous NULL Conventional Logic (NCL) Circuits

Due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, conventional automatic test pattern generation (ATPG) algorithms would fail when applied to asynchronous circuits, leading to poor fault coverage. This paper focuses on design for test (DFT) techniques aimed at making asynchronous NCL designs testable using existing DFT CAD tools with reasonable gate overhead, by enhancing controllability of feedback nets and observability for fault sites that are flagged unobservable. The proposed approach performs scan and test points insertion on NCL designs using custom ATPG library. The approach has been automated, which is essential for large systems; and are fully compatible with industry standard tools

DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits

Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL convention logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an automatic DFT insertion flow (ADIF) methodology that performs scan and test point insertion on NCL designs to improve test coverage, using a custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs

Design for test techniques for asynchronous NCL designs and FPGAs

Testing of an electronic chip is an important step in the design process, as it can detect faults and ensure reliability. Design for Test (DFT) methods are used to modify existing designs to enable their testing by Automatic Test Pattern Generators. This thesis focuses on developing testing techniques for design automation of NULL Conventional Logic (NCL) circuits and for detection of capacitive crosstalk effects in Field Programmable Gate Arrays (FPGAs). A novel technique is developed for testing asynchronous NCL designs aimed at good fault coverage with acceptable gate overhead. The technique focuses on testing stuck-at-faults in the internal feedback paths of NCL primitive gates and global feedback paths of the design. Controllability of the feedback paths and observability of the fault sites are enhanced to improve the testability of the design. Observability of the fault sites is improved based on Sandia Controllability And Observability Program (SCOAP) values, in order to reduce the gate overhead. This work also includes the automation of the testing process. A framework is proposed on the detection of capacitive crosstalk noise in FPGAs focusing on faults due to manufacture defects and process variations a framework. The approach is based on detecting crosstalk effects such as glitches and delayed transitions among the interconnect structure in FPGAs based on the Maximum Aggressor Fault model. Novel test architectures for Test Pattern Generator and Analyzer are presented. Enhancement in the existing cost function is also proposed to avoid the routing of interconnects affected by crosstalk noise in FPGAs --Abstract, page iii

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits